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68040 FEATURES
Selection of Processor Speeds: 25, 33MHz Military Temperature Range: -55C to +125C Packaging * 179 pin Ceramic PGA (P4) * 184 lead Ceramic Quad Flatpack, CQFP (Q4) 6-Stage Pipeline, 68030-Compatible IU 68881/68882-Compatible FPU Independent Instruction and Data MMUs Simultaneously Accessible, 4-Kbyte Physical Instruction Cache and 4-Kbyte Physical Data Cache Low-Latency Bus Acceses for Reduced Cache Miss Penalty Multimaster/Multiprocessor Support via Bus Snooping Concurrent IU, FPU, MMU, and Bus Controller Operation Maximizes Throughput
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32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface User Object-Code Compatible with all Earlier 68000 Microprocessors 4-GigaByte Direct Addressing Range
DESCRIPTION
The WC32P040 is a 68000-compatible, high-performance, 32-bit microprocessor. The WC32P040 is a virtual memory microprocessor employing multiple concurrent execution units and a highly intergrated architecture that provides very high performance in a monolithic HCMOS device. It has a 68030-compatible integer unit (IU) and two independent caches. The WC32P040 contains dual, independent, demand-paged memory management units (MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction and data caches. The WC32P040 has a 68881/68882-compatible floating-point unit (FPU).
FIGURE 1 - BLOCK DIAGRAM
INSTRUCTION DATA BUS
INSTRUCTION ATC
INSTRUCTION CACHE INSTRUCTION ADDRESS B U S C O N T R O L L E R
INSTRUCTION FETCH CONVERT DECODE EA CALCULATE EXECUTE EA FETCH EXECUTE WRITEBACK FLOATINGPOINT UNIT WRITEBACK INTEGER UNIT
INSTRUCTION MMU/CACHE/SNOOP CONTROLLER INSTRUCTION MEMORY UNIT
ADDRESS BUS
DATA BUS
DATA MEMORY UNIT DATA MMU/CACHE/SNOOP CONTROLLER
DATA ADDRESS
BUS CONTROL SIGNALS
DATA ATC
DATA CACHE
OPERAND DATA BUS
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FIGURE 2 - PIN CONFIGURATION FOR WC32P040-XXM, CQFP (Q4)
GND GND A31 A30 VCC A29 A28 GND A27 A26 VCC A25 A24 GND A23 A22 VCC A21 A20 GND A19 A18 VCC GND A17 A16 GND A15 A14 VCC A13 A12 GND A11 A10 GND VCC TT1 TT0 GND UPA1 UPA0 VCC CIOUT# IPEND# GND
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93
D0 D1 VCC GND D2 D3 GND D4 GND D5 VCC D6 D7 GND D8 D9 VCC GND D10 D11 GND D12 D13 VCC D14 D15 GND D16 D17 VCC GND D18 D19 GND D20 D21 VCC D22 VCC D23 GND D24 D25 GND VCC D26
TOP VIEW
92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47
D27 GND D28 D29 VCC D30 D31 GND GND A9 A8 VCC A7 A6 GND A5 A4 VCC A3 A2 GND A1 A0 VCC GND TM2 TM1 GND TM0 TLN1 VCC TLN0 SIZ0 GND R/W# LOCKE# VCC GND SIZ1 LOCK# GND MI# BR# VCC TS# BB#
Pin Group PLL Internal Logic Output Drivers 17, 22, 24
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RSTO# TD0 TD1 TCK GND TRST# TMS GND VCC MDIS# CDIS# RSTI# IPL2# IPL1# IPL0# GND GND BCLK VCC GND VCC GND PCLK GND GND DLE GND GND TCI# AVEC# TBI# VCC GND SC0 SC1 BG# TEA# TA# PST0 GND PST1 PST2 VCC PST3 TIP GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
GND 19, 21
Vcc
5, 8, 10, 27, 28, 33, 55, 68, 95, 108, 121, 130, 135, 162, 174 16, 20, 25, 40, 46, 52, 59, 65, 72, 78, 84, 85, 91, 98, 105, 112, 118, 125, 132, 139, 140, 146, 152, 158, 165, 171, 178, 184
9, 32, 56, 69, 81, 94, 100, 109, 122, 136, 149, 161, 175 43, 49, 62, 75, 88, 102, 115, 128, 143, 155, 168, 181
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FIGURE 3 - PIN CONFIGURATION FOR WC32P040-XXM, PGA (P4)
T TDO TRST# GND CDIS# IPL2# IPL1# IPL0# S IPEND# GND R CIOUT# VCC RTSO# GND Q UPA1 P A10 N A12 M A13 L A14 K A15 J A17 H A18 G A20 F A21 E A22 D A24 C A27 B A29 A A31 1 D3 2 D4 3 D5 4 D6 5 D7 6 D9 7 D10 8 D11 9 D12 10 D13 11 D14 12 D15 13 D17 14 D19 15 D20 16 D21 17 D24 18 GND D1 GND VCC GND D8 GND VCC GND D16 D18 GND VCC GND D22 GND D26 VCC D0 D2 VCC GND GND VCC GND VCC GND VCC GND VCC D23 D25 VCC D28 GND A30 D27 GND D31 A26 A28 D29 D30 A8 GND A25 A9 GND A7 VCC A23 A6 VCC A5 GND VCC VCC GND A4 A19 VCC A16 GND GND TM2 A2 A1 A3 GND GND VCC GND A0 VCC VCC GND VCC TM1 GND A11 R/W# GND TM0 TT1 TT0 SIZ1 SIZ0 TLN1 GND UPA0 MI# GND TLN0 VCC GND BCLK VCC PCLK GND GND VCC GND PST2 TIP# TS# VCC LOCKE# TDI TCK TMS MDIS# RSTI# VCC GND GND TBI# SC1 TEA# PST1 GND VCC GND LOCK# DLE TCI# AVEC# SC0 BG# TA# PST0 PST3 BB# BR#
BOTTOM VIEW
VCC
Pin Group PLL Internal Logic Output Drivers S9, R6, R10
GND R8, S8
Vcc
C6, C7, C9, C11, C13, K3, L3, M16, R4, R11, R13, S6, S10, T4 B2, B4, B6, B8, B10, B13, B15, B17, D2, D17, F2, F17, H2, H17, L2, L17, N2, N17, Q2, Q17, S2, S15, S17
C5, C8, C10, C12, C14, H3, H16, J3, J16, L16, M3, R5, R12 B5, B9, B14, C2, C17, G2, G17, M2, M17, R2, R17, S16
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DATA FORMATS
The WC32P040 supports the basic data formats of the 68000 family. Some data formats apply only to the IU, some only to the FPU, and some to both. In addition, the instruction set supports operations on other data formats such as memory addresses.
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ADDRESSSING
The WC32P040 supports the basic addressing modes of the 68000 family. The register indirect addressing modes support postincrement, predecrement, offset, and indexing. The program counter indirect mode also has indexing and offset capabilities.
DATA FORMATS
Operand Data Format Bit Bit Field Binary-Coded Decimal (BCD) Byte Integer Word Integer Long-Word Integer Quad-Word Integer 16-Byte Single-Precision Real Double-Precision Real Extended-Precision Real Size 1 Bit 1-32 Bits 8 Bits 8 Bits 16 Bits 32 Bits 64 Bits 128 Bits 32 Bits 64 Bits 80 Bits Supported In IU IU IU IU, FPU IU, FPU IU, FPU IU IU FPU FPU FPU Notes -- Field of Consecutive Bits Packed: 2 Digits/Byte; Unpacked: 1 Digit/Byte -- -- -- Any Two Data Registers Memory Only, Aligned to 16-Byte Boundary 1-Bit Sign, 8-Bit Exponent, 23-Bit Fraction 1-Bit Sign,11-Bit Exponent, 52-Bit Fraction 1-Bit Sign,15-Bit Exponent, 64-Bit Mantissa
ADDRESSING MODES
Addressing Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index Address Register Indirect with Index (8-Bit Displacement) Address Register Indirect with Index (Base Displacement) Memory Indirect Memory Indirect Postindexed Memory Indirect Preindexed Program Counter Indirect with Displacement Program Counter Indirect with Index PC Indirect with Index (8-Bit Displacement) PC Indirect with Index (Base Displacement) Program Counter Memory Indirect PC Memory Indirect Postindexed PC Memory Indirect Preindexed Absolute Absolute Short Absolute Long Immediate Syntax Dn An (An) (An) + - (An) (d16,An) (d8,An,Xn) (bd,An,Xn) ([bd,An],Xn,od) ([bd,An,Xn],od) (d16,PC) (d8,PC,Xn) (bd,PC,Xn) ([bd,PC],Xn,od) ([bd,PC,Xn],od) (xxx).W (xxx).L #
INSTRUCTION SET SUMMARY
Opcode ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ANDI to CCR ANDI to SR Operation BCD Source + BCD Destination + X Source + Destination Source + Destination Destination Destination Destination Destination Destination Syntax ABCD Dy,Dx ABCD -(Ay),-(Ax) ADD ,Dn ADD Dn, ADDA ,An ADDI #, ADDQ #, ADDX Dy,Dx ADDX -(Ay),-(Ax) AND ,Dn AND Dn, ANDI #, ANDI #,CCR ANDI #,SR SR
Immediate Data + Destination Immediate Data + Destination Source + Destination + X Source Destination
Destination Destination Destination
Immediate Data Destination Source CCR CCR If supervisor state then Source SR else TRAP
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INSTRUCTION SET SUMMARY (contd)
Opcode ASL,ASR Operation Destination Shifted by count Destination Syntax ASd Dx,Dy(1) ASd #,Dy(1) ASd (1) Bcc PC Z; (bit number) of Destination BCHG Dn, BCHG #, BCLR Dn, BCLR #, BFCHG {offset:width} BFCLR {offset:width} BFEXTS {offset:width}, Dn BFEXTU {offset:width}, Dn Dn BFFFO {offset:width}, Dn BFINS Dn, {offset:width} BFSET {offset:width} BFTST {offset:width} BKPT # BRA BSET Dn, BSET #, PC BSR BTST Dn, BTST #, cc; CAS Dc,Du,
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Bcc BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BRA BSET BSR BTST CAS
It condition true then PC + dn
~(bit number of Destination) ~(bit number ot Destination)
~(bit number ot Destination) Z; 0 bit number ot Destination ~(bit field ot Destination) 0 bit field of Destination Dn Dn bit field of Destination
bit field of Source bit offset of Source
bit offset of Source Bit Scan Dn 1s bit field of Destination bit field of Destination
bit field of Destination Run breakpoint acknowledge cycle; TRAP as illegal instruction PC+dn PC
~(bit number ot Destination) Z; 1 bit number of Destination SP - 4 SP; PC (SP); PC + dn Z
-(bit number of Destination)
CAS Destination - Compare Operand if Z, Update Operand Destination else Destination Compare Operand CAS2 Destination 1 - Compare 1 cc; if Z, Destination 2 - Compare cc; if Z, Update 1 Destination 1; Update 2 Destination 2 else Destination 1 Compare 1; Destination 2 Compare 2 If Dn < 0 or Dn > Source then TRAP If Rn < LB or If Rn > UB then TRAP If supervisor state then invalidate selected cache lines else TRAP 0 Destination cc
CAS2
CAS2 Dc1-Dc2,Du1-Du2,(Rn1)-(Rn2)
CHK CHK2 CINV
CHK ,Dn CHK2 ,Rn CINVL , (An) CINVP , (An) CINVA CLR CMP ,Dn CMPA ,An CMPI #, CMPM (Ay)+,(Ax)+ CMP2 ,Rn CPUSHL , (An) CPUSHP , (An) CPUSHA
CLR CMP CMPA CMPI CMPM CMP2 CPUSH
Destination - Source Destination - Source
Destination - Immediate Data Destination - Source cc
Compare Rn < LB or Rn > UB and Set Condition Codes If supervisor state then it data cache push selected dirty data cache lines; invalidate selected cache lines else TRAP
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INSTRUCTION SET SUMMARY (contd)
Opcode DBcc Operation If condition false then (Dn-1 Dn; if (Dn -1 then PC + dn PC) Destination + Source Destination Syntax DBcc Dn,
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DIVS, DIVSL
DIVS.W ,Dn DIVS.L ,Dq DIVS.L ,Dr:Dq DIVSL.L ,Dr:Dq DIVU.W ,Dn DIVU.L ,Dq DIVU.L ,Dr:Dq DIVUL.L ,Dr:Dq EOR Dn, EORI #, EORI #,CCR
32 + 16 32 + 32 64 + 32 32 + 32 32 + 16 32 + 32 64 + 32 32 + 32
16r:16q 32q 32r:32q 32r:32q 16r:16q 32q 32r:32q 32r:32q
DIVU, DIVUL
Destination + Source
Destination
EOR EORI EORI to CCR
Source Destination Source CCR
Destination Destination
Immediate Data Destination CCR
EORI to SR
If supervisor state
EORI #,SR then Source SR SR else TRAP EXG Dx,Dy EXG Ax,Ay EXG Dx,Ay EXG Ay,Dx Destination EXT.W Dn EXT.L L Dn EXTB.L Dn extend byte to word extend word to long word extend byte to long word
EXG
Rx
Ry
EXT,EXTB
Destination Sign - Extended
FABS
Absolute Value of Source
FPn
FABS. ,FPn FABS.X FPm,FPn FABS.X FPn FrABS. ,FPn(2) FrABS.X FPm,FPn(2) FrABS.X FPn(3) FADD.,FPn FADD.X FPm,FPn FrADD. ,FPn(2) FrADD.X FPm,FPn(2) FBcc.SIZE
FADD
Source + FPn
FPn
FBcc FCMP FDBcc
If condition true then PC + dn FPn - Source
PC FCMP. ,FPn FCMP.X FPm,FPn FDBcc Dn,
It condition true then no operation else Dn-1 Dn if Dn -1 then PC + dn PC else execute next instruction FPn + Source FPn
FDIV
FDIV. ,FPn FDIV.X FPm,FPn FrDIV. ,FPn(2) FrDIV.X FPm,FPn(2) FMOVE. ,FPn FMOVE. FPM, FMOVE.P FPm,{Dn} FMOVE.P FPm,{#k} FrMOVE. ,FPn(2)
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FMOVE
Source
Destination
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INSTRUCTION SET SUMMARY (contd)
Opcode Operation Syntax
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FMOVE FMOVEM
Source
Destination
FMOVE.L ,FPcr FMOVE.L FPcr, FMOVEM.X ,(3) FMOVEM.X Dn, FMOVEM.X ,(3) FMOVEM.X ,Dn FMOVEM.L ,(4) FMOVEM.L ,(4) FMUL. ,FPn FMUL.X FPm,FPn FrMUL ,FPn(2) FrMUL.X FPm,FPn(3) FNEG. ,FPn FNEG.X FPm,FPn FNEG.X FPn FrNEG. ,FPn(2) FrNEG.X FPm,FPn(2) FrNEG.X FPn(2) FNOP FRESTORE Internal State
FSAVE State Frame FScc.SIZE
Register List Destination Source Register List
FMOVEM FMUL
Register List Destination Source Register List Source x FPn FPn
FNEG
-(Source)
FPn
FNOP FRESTORE
None If in supervisor state then FPU State Frame else TRAP
If in supervisor state then FPU Internal State else TRAP If condition true then 1s Destination else 0s Destination FPn / Source Source x FPn FPn FPn FPn
FSAVE
FScc
FSGLDIV FSGLMUL FSQRT
FSGLDIV. ,FPn FSGLDIV.X FPm,FPn FSGMUL. ,FPn FSGLMUL.X FPm, FPn FSQRT. ,FPn FSQRT.X FPm,FPn FSQRT.X FPn FrSQRT. ,FPn FSUB.X FPm,FPn FrSUB. ,FPn(2) FrSUB.X FPm,FPn3(2) FTRAPcc FTRAPcc.W # FTRAPcc.L # FPCC FTST.dmt> FTST.X FPm ILLEGAL
Square Root of Source
FSUB
FPn - Source
FPn
FTRAPcc
If condition true then TRAP Condition Codes tor Operand
FTST ILLEGAL
SSP - 2 SSP; Vector Offset (SSP); SSP - 4 SSP; PC (SSP); SSp - 2 SSP; SR (SSP) Illegal Instruction Vector Address PC Destination Address PC
JMP
JMP
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INSTRUCTION SET SUMMARY (contd)
JSR Opcode LEA LINK LSL,LSR SP - 4 SP; PC (SP) Destination Address PC Operation An (SP) SP Destination JSR Syntax LEA ,An LINK An,dn LSd Dx,Dy(1) LSd #,Dy(1) LSd (1) MOVE , MOVEA , An MOVE CCR, MOVE ,CCR MOVE SR,
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SP - 4 SP;An SP An, SP + d
Destination Shifted by count
MOVE MOVEA MOVE from CCR MOVE to CCR MOVE from SR
Source Source CCR Source
Destination Destination Destination CCR
If supervisor state then SR Destination else TRAP If supervisor state then Source SR else TRAP It supervisor state then USP An or An else TRAP Source block USP
MOVE to SR
MOVE ,SR
MOVE USP
MOVE USP,An MOVE An,USP MOVE16 (Ax)+, (Ay)+(5) MOVE16 (xxx).L, (An) MOVE16 (An), (xxx).L MOVE16 (An)+, (xxx).L Rc else TRAP MOVEC Rc,Rn MOVEC Rn,Rc MOVEM ,(3) MOVEM ,(3) MOVEP Dx,(dn,Ay) MOVEP (dn,Ay),Dx
MOVE1 6
Destination block
MOVEC MOVEM MOVEP
If supervisor state then Rc Registers Destination Source Registers Source Destination
Rn or Rn
MOVEQ MOVES
Immediate Data
Destination Rn
MOVEQ #,Dn MOVES Rn, MOVES ,Rn MULS.W ,Dn MULS.L ,Dh-Dl MULU.W ,Dn MULU.L ,DI MULU.L ,Dh-DI NBCD NEG NEGX NOP NOT OR ,Dn OR Dn,
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If supervisor state then Rn Destination [DFC) or Source [SFC] else TRAP Source x Destination Destination
MULS
16 x 16 32 x 32 32 x 32 16 x 16 32 x 32 32 x 32
32 32 64 32 32 64
MULU
Source x Destination
Destination
NBCD NEG NEGX NOP NOT OR
0 - (Destination10) - X 0 - (Destination) None ~ Destination 0 - (Destination) - X
Destination Destination
Destination
Destination Destination
Source V Destination
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INSTRUCTION SET SUMMARY (contd)
Opcode Operation Syntax
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ORI ORI to CCR ORI to SR
Immediate Data V Destination Source V CCR CCR SR If supervisor state then Source V SR else TRAP
Destination
ORI #, ORI #,CCR ORI #,SR
PACK PEA PFLUSH
Source (Unpacked BCD) + adjustment SP - 4 SP; (SP)
Destination (Packed BCD)
PACK -(Ax),-(Ay),#(adjustment) PACK Dx,Dy,#(adjustment) PEA PFLUSH (An) PFLUSHN (An) PFLUSHA PFLUSHAN
If supervisor state then invalidate instruction and data ATC entries for destination address else TRAP If supervisor state then logical address status else TRAP If supervisor state then Assert RSTO# Line else TRAP Destination Rotated by count Destination Destination MMUSR; entry ATC
PTEST
PTESTR (An) PTESTW (An) RESET
RESET
ROL, ROR ROXL, ROXR
ROd Rx,Dy(1) ROd #,Dy(1) ROXd Dx,Dy(1) ROXd #,Dy(1) ROXd (1) RTD #(dn) RTE SP;
Destination Rotated with X by count
RTD RTE
(SP)
PC; SP + 4 + dn
SP
If supervisor state then (SP) SR; SP + 2 SP; (SP) PC; SP + 4 restore state and deallocate stack according to (SP) else TRAP (SP) (SP) (SP) CCR; SP + 2 SP; PC; SP + 4 SP PC; SP + 4 SP Destination
RTR RTS SBCD Scc
RTR RTS SBCD Dx,Dy SBCD -(Ax),-(Ay) Scc
Destination10 - Source10 - X If condition true then 1s Destination else 0s Destination If supervisor state then Immediate Data elseTRAP Destination - Source Destination - Source
STOP
STOP # SR; STOP Destination Destination Destination Destination SUB ,Dn SUB Dn, SUBA ,An SUBI #, SUBQ #,
SUB SUBA SUBI SUBQ
Destination - Immediate Data Destination - Immediate Data
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INSTRUCTION SET SUMMARY (contd)
Opcode Operation Syntax
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SUBX SWAP TAS TRAP
Destination - Source - X Register 31 - 16
Destination
SUBX Dx,Dy SUBX (Ax), (Ay) SWAP Dn TAS TRAP #
Register 15 - 0
Destination Tested Condition Codes; 1 bit 7 of Destination SSP - 2 SSP; Format + Offset (SSP) SSP - 4 SSP; PC (SSP); SSP - 2 SSP; SR (SSP); Vector Address PC If cc then TRAP If V then TRAP Destination Tested An SP; (SP) Condition Codes An; SP + 4 SP Destination (Unpacked BCD)
TRAPcc
TRAPcc TRAPcc.W # TRAPcc.L # TRAPV TST UNLK An UNPACK -(Ax ), -(Ay), # (adjustment) UNPACK Dx,Dy, #(adjustment)
TRAPV TST UNLK UNPK
Source (Packed BCD) + adjustment
NOTES: 1. Where d is direction, left or right. 2. Where r is rounding precision, single or double precision. 3. List refers to register. 4. List refers to control registers only. 5. MOVE16 (ax)+, (ay)+ is functionally the same as MOVE16 (ax), (ay)+ when ax = ay. The address register is only incremented once, and the line is copied over itself rather than to the next line.
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FIGURE 4 - FUNCTIONAL SIGNAL GROUPS
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ADDRESS BUS DATA BUS
A31-A0 D31-D0
SC0 SC1 MI# BR# BG# BB# CDIS# MDIS# RSTI# RSTO# IPL0# IPL1# IPL2# IPEND# AVEC# PST0 PST1 PST2 PST3 BCLK PCLK TCK TMS TDI TDO TRST# Vcc GND
BUS SNOOP CONTROL AND RESPONSE
BUS ARBITRATION
TRANSFER ATTRIBUTES
TT0 TT1 TM0 TM1 TM2 TLN0 TLN1 UPA0 UPA1 R/W SIZ0 SIZ1 LOCK LOCKE CIOUT
PROCESSOR CONTROL
INTERRUPT CONTROL
MASTER TRANSFER CONTROL
TS TIP TA TEA TCI TBI DLE
STATUS AND CLOCKS
SLAVE TRANSFER CONTROL
TEST
POWER SUPPLY
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SIGNAL INDEX
Signal Name Address Bus Data Bus Transfer Type Transfer Modifier Transfer Line Number User-Progammable Attributes Read/Write Transfer Size Bus Lock Bus Lock End Cache Inhibit Out Transfer Start Transfer on Progress Transfer Acknowledge Transfer Error Acknowledge Transfer Cache Inhibit Transfer Burst Inhibit Data Latch Enable Snoop Control Memory Inhibit Bus Request Bus Grant Bus Busy Cache Disable MMU Disable Reset In Reset Out Interrupt Priority Level Interrupt Pending Autovector Processor Status Processor Clock Test Clock Test Mode Select Test Data Input Test Data Output Test Reset Power Supply Ground Mnemonic A31-A0 D31-D0 TT1,TT0 TM2-TM0 TLN1-TLN0 UPA1,UPA0 R/W# SIZ0/SIZ1 LOCK# LOCKE# CIOUT# TS# TIP# TA# TEA# TCI# TBI# DLE SC1,SC0 MI# BR# BG# BB# CDIS# MDIS# RSTI# RSTO# IPL2#-IPL0# IPEND# AVEC# PST3-PST0 PCLK TCK TMS TDI TDO TRST# Vcc GND Function 32-bit address bus used to address any of 4-Gbytes. 32-bit data bus used to transfer up to 32 bits of data per bus transfer.
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Indicates the general transfer type: normal, MOVE16, alternate logical function code, and acknowledge. Indicates supplemental information about the access. Indicates which cache line in a set is being pushed or loaded by the current line transfer. User-defined signals, controlled by the corresponding user attribute bits from the address translation entry. Identifies the transfer as a read or write. Indicates the data transfer size. These signals, together with A0 and A1, define the active sections of the data bus. Indicates a bus transfer is part of a read-modify-write operation, and the sequence of transfers should be interrupted. Indicates the current transfer is the last in a locked sequence of transfers. Indicates the processor will not cache the current bus transfer. Indicates the beginning of the bus transfer. Asserted for the duration of a bus transfer. Asserted to acknowledge a bus transfer. Indicates an error condition exists for a bus transfer. Indicates the current bus transfer should not be cached. Indicates the slave cannot handle a line burst access. Alternate clock input used to latch input data when the processor is operating in DLE mode. Indicates the snooping operation required during an alternate master access. Inhibits mem ory devices from responding to an alternate master access during snooping operations. Asserted by the processor to request bus mastership. Asserted by an arbiter to grant bus mastership to the processor. Asserted by the current bus master to indicate it has assumed ownership of the bus. Dynamically disables the internal caches to assist emulator support. Disables the translation mechanism of the MMUs. Processor reset. Asserted during execution of a RESET instruction to reset external devices. Provides an encoded interrupt level to the processor. Indicates an interrupt is pending. Used during an interrupt acknowledge transfer to request internal generation of the vector number. Indicates internal processor status. Clock input used for internal logic timing. The PCLK frequency is exactly 2 x the BLCK frequency. Clock signal for the IEEE P1149.1 Test Access Port (TAP). Selects the principle operations of the test-support circuitry. Serial data input for the TAP. Serial data output for the TAP. Provides an asynchronous reset of the TAP controller. Power supply. Ground connection.
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MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Maximum Operating Temperature Minimum Operating Temperature Storage Temperature Symbol VCC VIN TJ TA TSTG Value -0.3 to +7.0 -0.5 to +7.0 +125 -55 -55 to +150 Unit V V C C C Buffer Mode
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POWER DISSIPATION
25 MHz 4.9W 5.1W 6.5W 33 MHz 6.2W 6.6W 8.0W Small Unterminated, IOL = IOH = 5mA Large Unterminated, IOL = IOH = 5mA Large Terminated, 50 , 2.5V, IOL = IOH = 55mA
THERMAL CHARACTERISTICS
Parameter Thermal Resistance, Junction to Case - PGA Package Symbol JC Value 3.0 Rating C/W
DC ELECTRICAL SPECIFICATIONS
VCC = 5.0 VDC 5%
Characteristics Input High Voltage Input Low Voltage Undershoot Input Leakage Current @ 0.5/2.4V High-Z (Off State) Leakage Current @ 0.5/2.4 V Signal Low Input Current, VIL = 0.8V Signal High Input Current, VIH = 2.0V Output High Voltage, IOH = 5mA (Small Buffer Mode) Output Low Voltage, IOL = 5mA (Small Buffer Mode) Output High Voltage, IOH = 55mA (Large Buffer Mode) Output Low Voltage, IOL = 55mA (Large Buffer Mode) Capacitance (1), VIN = 0V, f = 1MHz
NOTE: 1. Capacitance is guaranteed by design but not tested.
Symbol VIH VIL -- AVEC#, BCLK, BG#, CDIS#, MDIS#, IPLx#, PCLK, RSTI#, SCx, TBI#, TMx, TLNx, TCI#, TCK, TEA# An, BB#, CIOUT#, Dn, LOCK#, LOCKE#, R/W#, SIZX, TA#, TDO, TIP#, TMx, TLNx, TS#, TTx, UPAx TMS, TDI, TRST# TMS, TDI, TRST# IIN ITSI IIL IIH VOH VOL VOH VOL CIN
Min 2.0 GND -- 20 20 -1.1 -0.94 2.4 -- 2.4 -- --
Max Vcc 0.8 0.8 20 20 -0.18 -0.16 -- 0.5 -- 0.5 20
Unit V V V A A mA mA V V V V pF
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CLOCK AC TIMING SPECIFICATIONS (SEE FIGURE 5)
Characteristic Frequency of Operation PCLK Cycle Time PCLK Rise Time PCLK Fall Time PCLK Duty Cycle Measured at 1.5V PCLK Pulse Width High Measured at 1.5V PCLK Pulse Width Low Measured at 1.5V BCLK Cycle Time BCLK Rise and Fall Time BCLK Duty Cycle Measured at 1.5V BCLK Pulse Width High Measured at 1.5V BCLK Pulse Width Low Measured at 1.5V PCLK, BCLK Frequency Stability PCLK and BCLK Skew
NOTES: 1. Specification value at maximum frequency of operation.
Specification
25 MHz Min 20 20 -- -- 47.50 9.50 9.50 40 -- 40 16 16 -- -- Max 25 25 1.7 1.6 52.50 10.50 10.50 50 4 60 24 24 1000 9 Min 20 15 -- -- 46.67 7 7 30 -- 40 12 12 -- --
33 MHz Max 33 25 1.7 1.6 53.33 8 8 50 3 60 18 18 1000 n/a
Unit MHz ns ns ns % ns ns ns ns % ns ns ppm ns
1 2 3 4 4A (1) 4B (1) 5 6,7 8 8A (1) 8B (1) 9 10
FIGURE 5 - CLOCK INPUT TIMING DIAGRAM
1
4A 4B 2 3
PCLK
VM
ViH VIL
10
10
6
7
BCLK
8A 5
VM
8B
ViH Vil
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OUTPUT AC TIMING SPECIFICATIONS (SEE FIGURE 6-10)
25 MHz Characteristic Specification Large (1) Min BCLK to Address CIOUT#, LOCK#, LOCKE#, R/W#, SIZx, TLN, TMx, TTx, UPAx Valid BCLK to Output Invalid (Output Hold) BCLK to TS# Valid BCLK to TIP# Valid BCLK to Data Out Valid BCLK to Data Out Invalid (Output Hold) BCLK to Output Low Inpedance BCLK to Data-Out High Impedance BCLK to Multiplexed Address Valid BCLK to Multiplexed Address Driven BCLK to Multiplexed Address High Impedance BCLK to Multiplexed Data Valid BCLK to Multiplexed Data Driven BCLK to Address, CIOUT#, LOCK#, LOCKE#, R/W#, SIZx, TS#, TLNx, TMx, TTx, UPAx High Impedance BLCLK to BB#, TA#, TIP# High Impedance BCLK to BR#, BB# Valid BCLK to MI# Valid BCLK to TA# Valid BCLK to IPEND#, PSTx, RSTO# Valid 11 (3) 12 13 14 18 (4) 19 (4) 20 (3,4) 21 (5) 26 (3) 27 (3,5) 28 (3,4,5) 29 (4,5) 30 (4) 38 (3) 39 40 43 48 50 9 9 9 9 9 9 9 9 19 19 9 19 19 9 19 9 9 9 9
3.
33 MHz Small (2) Large (1) Min 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 14 14 6.50 14 14 6.50 14 6.50 6.50 6.50 6.50 Max 18 - 18 18 20 - - 17 26 - 15 20 28 15 23 18 18 18 18 Small (2) Min 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 14 14 6.50 14 14 6.50 14 6.50 6.50 6.50 6.50 Max 25 - 25 25 27 - - 17 33 - 15 20 35 15 23 25 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Max 21 - 21 21 23 - - 20 31 - 18 - 33 18 28 21 21 21 21
Min 9 9 9 9 9 9 9 9 19 19 9 19 19 9 19 9 9 9 9
Max 30 - 30 30 32 - - 20 40 - 18 - 42 18 28 30 30 30 30
NOTES: 1. Output timing is specified for a valid signal measured at the pin. Large buffer timing is specified driving a 50 transmission line with a length characterized by a 2.5ns one-way propagation delay, terminated through 50 to 2.5V. Large buffer output impedance is 4-12, resulting in incident wave switching for this environment. All large buffer outputs must be terminated to guarantee operation. 2. Small buffer timing is specified driving an unterminated 30 transmission line with a length characterized buy a 2.5ns one-way propagation delay. Small buffer output impedance is typically 30; the small buffer specifications include approximately 5ns for the signal to propagate the length of the transmission line and back.
4.
5.
Timing specifications 11, 20, and 38 for address bus output timinng apply when normal bus operation is selected. Specifications 26, 27, and 28 should be used when the multiplexed bus mode of operation is enabled. Timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected. Specifications 28 and 29 should be used when the multiplexed bus mode of operation is enabled. Timing specifications 21, 27, 28, and 29 are measured from BCLK edges. By design, the 68040 cannot drive address and data simultaneously during multiplexed operations.
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INTPUT AC TIMING SPECIFICATIONS (SEE FIGURE 6-10)
25 MHz Characteristic Data-In Valid to BCLK (Setup) BCLK to Data-In Valid (Hold) BCLK to Data-In High Impedance (Read Followed by Write) TA# Valid to BCLK (Setup) TEA# Valid to BCLK (Setup) TCI# Valid to BCLK (Setup) TBI# Valid to BCLK (Setup) BCLK to TA#, TEA#, TCI#, TBI# Invalid (Hold) AVEC# Valid to BCLK (Setup) BCLK to AVEC# Invalid (Hold) DLE Width High Data-In Valid to DLE (Setup) DLE to Data-In Invalid (Hold) BCLK to DLE Hold DLE High to BCLK Data-In Valid to BCLK (DLE Mode Setup) BCLK to Data-In Invalid (DLE Mode Hold) BB# Valid to BCLK (Setup) BG# Valid to BCLK (Setup) CDIS#, MDIS# Valid to BCLK (Setup) IPLx# Valid to BCLK (Setup) BCLK to BB#, BG#, CDIS#, IPLx#, MDIS# Invalid (Hold) Address Valid to BCLK (Setup) SIZx Valid BCLK (Setup) TTx Valid to BCLK (Setup) R/W Valid to BCLK (Setup) SCx Valid to BCLK (Setup) BCLK to Address, SIZx, TTx, R/W#, SCx Invalid (Hold) TS# Valid to BCLK (Setup) BCLK to TS# Invalid (Hold) BCLK to BB# High Impedance (MC68040 Assumes Bus Mastership) RSTI# Valid to BCLK BCLK to RSTI# Invalid Mode Select Setup to RSTI# Negated RSTI# Negated to Mode Selects Invalid Specification Min 15 16 17 22A 22B 22C 22D 23 24 25 31 32 33 34 35 36 37 41A 41B 41C 41D 42 44A 44B 44C 44D 44E 45 46 47 49 51 52 53 54 5 4 - 10 10 10 11 2 5 2 8 2 8 3 16 5 4 7 8 10 4 2 8 12 6 6 10 2 5 2 - 5 2 20 2 Max - - 49 - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 - - - - Min 4 4 - 10 10 10 10 2 5 2 8 2 8 3 12 5 4 7 7 8 3 2 7 8 8.5 5 11 2 9 2 - 4 2 20 2 Max - - 36.5 - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 33 MHz Unit
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FIGURE 6 - DRIVE LEVELS AND TEST POINTS FOR AC SPECIFICATONS
TO 2.4V
BCLK DRIVE TO 0.5V OUTPUTS (1)
1.5V A B 2.0V
1.5V
2.0V VALID OUTPUT n 0.8V
VALID 0.8V OUTPUT n + 1 C D VALID INPUT 2.0V 0.8V
INPUTS (2)
DRIVE TO 2.4V DRIVE TO 0.5V
2.0V 0.8V
2.0V RSTI# (3) F E IPLX#, CDIS#, MDIS# 2.0V 0.8V
NOTE: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. This input timing is applicable to all parameters specified relative to the rising edge of the clock. 3. This timing is applicable to all parameters specified relative to the negation of the RSTI# signal. LEGEND: A. Maximum output delay specification. B. Minimum output hold time. C. Minimum input setup time specification. D. Minimum input hold time specification. E. Mode select setup time to RSTI# negated. F. Mode select hold time to RSTI# negated.
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FIGURE 7 - READ/WRITE TIMING DIAGRAM
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BCLK 11 A31-A0 TRANSFER ATTRIBUTES 13 TS# 14 TIP# 15 16 D31-D0 IN (READ) 18 D31-D0 OUT (WRITE) TA# 20 21 19 23 12 12 12
22
TEA#
TCI#
TBI# 24 AVEC# 25
NOTE: Transfer Attribute Signals = UPAx, SIZx, TTx, TMx, TLNx, R/W#, LOCK#, LOCKE#, CIOUT#
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FIGURE 8 - BUS ARBITRATION TIMING DIAGRAM
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BCLK 38 A31-A0 TRANSFER ATTRIBUTES 11
LOCK#, LOCKE# 13 39 TIP# D31-D0 OUT (WRITE) 40 BR# 41 BG# 39 BB OUT# 12 43 MI# 20 12 40 42 12 12 21 14 20
TS#
NOTE: Transfer Attribute Signals = UPAx, SIZx, TTx, TMx, TLNx, R/W#, CIOUT#
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FIGURE 9 - SNOOP HIT TIMING DIAGRAM
BCLK 44 A31-A0 IN SIZx, TTx, R/W# IN SC1, SC0 46 TS# IN 12 MI 43 D31-D0 OUT (ALT. MASTER WRITE) D31-D0 OUT (ALT. MASTER READ) TA# OUT 41 BB# IN 48 42 15 15 21 18 20 12 49 19 47 45
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FIGURE 10 - SNOOP MISS TIMING DIAGRAM
BCLK 44 A31-A0 IN SIZx, TTx, R/W# IN SC1, SC0 SNOOP 46 TS# IN 43 MI# 22 TA# 43 12 23 47 45
TEA#
TBI# 41 BB# IN 42
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FIGURE 11 - OTHER SIGNAL TIMING DIAGRAM
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BCLK 50 IPEND# 12
RSTO#
PST3-PST0 12 CDIS# 41 MDIS# 41 42 IPL2#-IPL0# 51 RSTI# 54 53 CDIS#, MDIS# IPL2#-IPL0# 52 42
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FIGURE 12 179 PIN GRID ARRAY, PGA (P4)
47.25 (1.860) 0.50 (0.020) SQ.
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4.07 (0.160) 0.26 (0.010) T S R Q P N M L K J H G F E D C B A
2.54 (0.100)
2.54 (0.100)
0.46 (0.018) 0.05 (0.002)
PIN A1 INDICATOR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.92 (0.115) 0.13 (0.005)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
FIGURE 13 184 LEAD, CERAMIC QUAD FLAT PACK, CQFP (q4)
34.93 (1.375) 0.55 (0.022) 31.31 (1.232) 0.44 (0.017) SQ.
138 93
4.08 (0.161) 0.80 (0.031)
139
92
0.20 (0.008) REF 34.93 (1.375) 0.55 (0.022) 29.25 (1.152) REF 0-4
0-8 4.08 (0.161) 0.80 (0.031)
0.76 (0.030) 0.16 (0.006) 0.80 (0.031) 0.15 (0.006) 0.80 (0.031) REF 1.80 (0.071) REF
DETAIL A
184
47
1
0.65 (0.026) 0.33 (0.013)
46
0.75 (0.030)
DETAIL A
0.20 (0.008) 0.05 (0.002)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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ORDERING INFORMATION
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W C 32 P040 - X X M
DEVICE GRADE: M = Military Temperature PACKAGE: P4 = 179 Pin Ceramic PGA Q4 = 184 Lead Ceramic Quad Flatpack, CQFP Operating Frequency in MHz 68040 32 bit Wide MICROCONTROLLER WHITE MICROELECTRONICS -55C to +125C
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